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DS707 april 19, 2010 www.xilinx.com 1 product specification ? copyright 2007-2010 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise and other designated brands included herein ar e trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. introduction the logicore ip xps ps2 controller is a plb (processor local bus) slave that is designed to control ps2 devices such as keyb oard and mouse. the ps2 protocol is a simple bidirectional serial protocol. features ? connects as a 32-bit slave on plb v4.6 bus of 32, 64 or 128 bit data width ? configurable as single or dual port ps2 controller ? supports two ps2 devices, each controlled by separate set of eight byte-wide registers ? two separate interrupts for each of the ports 0 logicore ip xps ps2 controller (v1.01b) DS707 april 19, 2010 00 product specification logicore? facts core specifics supported device family spartan ? -6, virtex ? -6/-6cx, spartan-3, spartan-3a, spartan-3e, automotive spartan-3/3e/3a/3a dsp, spartan-3 adsp, virtex-4, qvirtex-4, qrvirtex-4,virtex-5/5fx version of core xps_ps2 v1.01b resources used min max slices see ta bl e 1 4 , ta bl e 1 5 , ta bl e 1 6 , ta b l e 1 7 , and ta b l e 1 8 luts ffs block rams n/a special features n/a provided with core documentation product specification design file formats vhdl constraints file n/a verification n/a instantiation template n/a reference designs & application notes n/a design tool requirements xilinx implementation to o l s ise 12.1 verification mentorgraphics modelsim 6.5c and above simulation mentorgraphics modelsim 6.5c and above synthesis xst support provided by xilinx, inc.
DS707 april 19, 2010 www.xilinx.com 2 product specification logicore ip xps ps2 controller (v1.01b) functional description the xps ps2 controller is a slave ip core designed to co ntrol two ps2 devices such as a keyboard and a mouse. to control the two ps2 devices, it uses simple state machines and shift registers. each of the ps2 ports is controlled by a separate set of four byte-wide register s. for transmitting data, a byte is written to the transmit register and then the serial interface engine serializes the data and transmits to the ps2 device. transmit status registers and interrupts indicate whether the transmission is complete and if there are any errors reported. while receiving data, the serial interface engine receives serial data from the ps2 device and writes into the receive register. similar to the transmit status registers, receive status registers and inte rrupts indicate whether data has been received from the ps2 device. any errors in the received data are also reported. the xps ps2 controller generates interrupts upon various transmit and receive conditions.the xps ps2 contro ller can be operated in a polled mode or an interrupt driven mode. ps2 communication the ps2 protocol consists of host-to-device and device-to-host commu nication. in the description below "host" implies the xps ps2 controller and "device" implies any ps2 device, which would be a keyboard or a mouse. the ps2 protocol is a bidirectional sy nchronous serial protocol. the data an d the clock are the two signals through which communication between the device and the host happen s. the host is given the ul timate control of the data bus. the basic states which can be defined based on the status of the data and clock lines are: ? idle state - data is high and clock is high. this is the only state where the ps2 device is allowed to start transmission of data (during device-to-host communication). ? communication inhibited state - data high and clock lo w. the device always generates the clock signal. but since the host has the ultimate cont rol of the bus and may inhibit communication anytime, it must pull the clock signal low and inhibit the transmission by the device and then initiate transmission from its side. ? host request-to-send state - data is low and clock is high. the host after inhibiti ng the communication, will pull the data line low and release the clock inline, signalling the device that host would transmit data. all the data is transmitted one byte at a time and each byte is sent in a frame consisting of 11-12 bits (depending on whether it is host-to-device or device -to-host communication). these bits are: ? 1 start bit. this is always 0 ? 8 data bits, least significant bit first ? 1 parity bit (odd parity) ? 1 stop bit. this is always 1 ? 1 acknowledge bit (host-to-device communication only) the data sent from the device to host is read on the falling edge and the data sent from the host to device is read on the rising edge. the clock frequency must be in the range 10-16.7 khz. this means clock must be high for 30 - 50 microseconds and low for 30 - 50 microseconds. the keyboa rd, mouse or host emulator should modify/sample the data line in the middle of each cell, i.e. 15 - 25 microseconds after the appropriate clock transition. device-to-host communication the device-to-host communication ha ppens over 11-bit frames. when the keyboard or mouse wants to send information, it first checks the clock line to make sure it's at a high logic level. if it's not, the host is inhibiting communication and the device must buffer any to-be-sent da ta until the host releases clock. the clock line must be continuously high for at least 50 microseconds before the device can begin to transmit data. the host may inhibit communication at any time by pulling the clock line lo w for at least 100 microseconds. if a
DS707 april 19, 2010 www.xilinx.com 3 product specification logicore ip xps ps2 controller (v1.01b) transmission is inhibited before the 11th clock pulse, th e device must abort the current transmission and prepare to retransmit the current "chunk" of data when host releases clock. a "chunk" of data could be a make code, break code, device id, mouse movement packet, etc. for example, if a keyboard is interrupted while sending the second byte of a two-byte break code, it will need to retransmit both bytes of that break code, not just the one that was interrupted. if the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the ps2 device does not need to retran smit any data. however, if new data is created that needs to be transmitted, it will have to be buffered until the host releases clock. figure 1 illustrates the above mentione d device-to-host communication. host-to-device communication the host-to-device communication happens over 12-bit fr ames. since the ps2 device always generates the clock signal, the host whenever it wants to send data, must inhibit communication by pulling the clock low for at least 100 microseconds. it must then apply a "request-to-send" by pulling data low while releasing the clock signal. the device should check for this state at intervals not to exceed 10 milliseconds. when the device detects this state, it will begin generating clock signals and clock in eight da ta bits and one stop bit. the host changes the data line only when the clock line is low, and data is read by the device when clock is high. after the stop bit is received, the device will acknowledge the received byte by bringing the data line low and generating one last clock pulse. if the host does not release the data line after the 11th clock puls e, the device will continue to generate clock pulses until the data line is released (the device will then generate an error.) the host may abort transmission at time before the 11th clock pulse (acknowledge bit) by holding clock low for at least 100 microseconds . there are two timings that are needed to be taken care by the state machines. the time it the device to begin generating clock pulses after the host initially takes the clock line low, which must be no greater than 15 milliseconds. and the time it takes for the packet to be se nt, which must be no greater than 2 milliseconds. if either of the above time limits is not met, the host should generate an error. if the command sent by the host requires a x-ref target - figure 1 figure 1: device-to-host communication clock data s tart data0 data1 data2 data4 data 3 data5 data6 data7 parity s top the d a t a line i s ch a nged b y the device when the clock i s low a nd i s re a d b y the ho s t when the clock i s high d s 707_01_041910
DS707 april 19, 2010 www.xilinx.com 4 product specification logicore ip xps ps2 controller (v1.01b) response, that response must be received no later than 20 milliseconds after the host releases the clock line. if this does not happen, the host should generate an error. the major interface and modules, for each of the ports, of the xps ps2 controller are shown in figure 3 and described in the subsequent sections. these modules are: ? plb interface module ? interrupt service controller ? serial interface engine (sie) ? internal registers x-ref target - figure 2 figure 2: host-to-device communication clock data clock data s tart data0 data1 data2 data4 data 3 data5 data6 data7 parity s top ack ho s t device a < 15m s b < 2m s e c > 100 us d s 707_02_041910
DS707 april 19, 2010 www.xilinx.com 5 product specification logicore ip xps ps2 controller (v1.01b) plb interface module the plb interface module is a bi-directional interface betw een xps ps2 controller ip core and the plb. to simplify the process of attaching a xps ps2 controller to the pl b, the core makes use of a portable, pre-designed bus interface called plb interface module, th at takes care of the bus interface sign als, bus protocols and other interface issues. the base element of the plb interface module is slave attachment, which provides the basic functionality of plb slave operation. x-ref target - figure 3 figure 3: xps ps2 controller block diagram plb interf a ce mod u le xp s p s 2 controller 6 b it s ip2intc_irpt_1 p s 2_2_data p s 2_2_clk p s 2_1_clk p s 2_1_data receiver d a t a regi s ter tr a n s mit d a t a regi s ter core s t a t us regi s ter intern a l regi s ter s p s port 1 2 p s 2 s oft re s et regi s ter tr a n s mitter s t a te m a chine receiver s t a te m a chine p s 2 port1 s ie w a tch dog timer s hift regi s ter s ip2intc_irpt_2 d s 707_02_0 3 2 3 09 6 b it s clock control s t a te m a chine w a tch dog timer s hift regi s ter s clock control s t a te m a chine glo ba l interr u pt regi s ter tr a n s mitter s t a te m a chine receiver s t a te m a chine interr u pt en ab le regi s ter interr u pt s t a t us regi s ter glo ba l interr u pt regi s ter interr u pt en ab le regi s ter interr u pt s t a t us regi s ter p s 2 s oft re s et regi s ter tr a n s mit d a t a regi s ter receive d a t a regi s ter core s t a t us regi s ter intern a l regi s ter s p s 2 p s 2 port 2 s ie plb port 1 interr u pt s ervice controller port 2 interr u pt s ervice controller port 2
DS707 april 19, 2010 www.xilinx.com 6 product specification logicore ip xps ps2 controller (v1.01b) interrupt service controller the interrupt service controller is a continuation of th e xilinx family of ibm coreconnect compatible logicore products. it provides interrupt capture support for th e connected ip function. the interrupts from xps ps2 controller are connected to the interrupt service controller and the corresponding bits in the interrupt status register get updated. interrupt service controller provides following functions: ? parameterized number of interrupts needed by the ip. ? provides both interrupt status regist er (isr) and interrupt enable register (ier) functions for the user ip. depending on which interrupt bits are enabled in the ier, the corresponding interrupts from the ip would be or-ed and a single interr upt would be generated. serial interface engine the serial interface engine has the following modules: ? transmit state machine - there are 2 separate transmit stat e machines for each of the ps2 ports. this helps each of the ports to transmit simultaneously irrespective of the other port. the transmit state machine serializes the data written into the transmit data register and sends it over the data line as per the ps2 protocol as mentioned above in the host-to-device communication section. ? receive state machine - there are 2 separate receive state machines for each of the ps2 ports. this helps each of the ports to receive simultaneously irrespective of the other port. the receive state machine does the serial-to-parallel conversion of the serial data received on the data line and writes into the receive data register and sends it over the data line as per th e ps2 protocol as mentioned above in the device-to-host communication section. ? shift registers - the parallel -to-serial and serial-to-parall el conversion of data by the transmit state machines and receive state machine respectively, is done by using these shift registers. ? clock control state machine - this stat e machine detects the rise and fall of the clock line. this edge detection is required for the transmit and receive state machines to perform the operation. th e ps2 protocol is greatly dependent on the edge of the clock. ? watch dog timer- the watch dog timer keeps a watch on the clock line while transmitting. if the clock line goes into the pull-up mode in between transmission, the watch dog timer se ts the corresponding interrupt. if there are no transitions on the clock for 200 micr oseconds, the watch timer would set the interrupt. internal registers the xps ps2 controller has eight internal registers, four registers for each of the ps2 ports. the whole operation happens through the internal registers. for transmitting data to the ps2 device, the data needs to be written into the transmit register and similarly the rece ive register would get updated as soon as the data is received from the ps2 device. a more detailed description of these registers is given in the xps ps2 controller register descriptions section.
DS707 april 19, 2010 www.xilinx.com 7 product specification logicore ip xps ps2 controller (v1.01b) xps ps2 controller i/o signals the xps ps2 controller i/o signal s are listed and described in table 1 . all signals are active high. ta bl e 1 : xps ps2 controller i/o signal description port signal name interface i/o initial state description system signals p1 splb_clk system i - plb clock p2 splb_rst system i - plb reset plb slave interface input signals p3 plb_abus[0: c_splb_awidth - 1] plb i - plb address bus p4 plb_pavalid plb i - plb primary address valid p5 plb_masterid[0: c_splb_mid_width - 1] plb i - plb current master identifier p6 plb_rnw plb i - plb read not write p7 plb_be[0: (c_splb_dwidth/8) - 1] plb i - plb byte enables p8 plb_size[0:3] plb i - plb si ze of requested transfer p9 plb_type[0:2] plb i - plb transfer type p10 plb_wrdbus[0: c_splb_dwidth - 1] plb i - plb write data bus unused plb slave interface input signals p11 plb_uabus[0: 31] plb i - plb upper address bits p12 plb_savalid plb i - plb secondary address valid p13 plb_rdprim plb i - plb secondary to primary read request indicator p14 plb_wrprim plb i - plb secondary to primary write request indicator p15 plb_abort plb i - plb abort bus request p16 plb_buslock plb i - plb bus lock p17 plb_msize plb i - plb data bus width indicator p18 plb_lockerr plb i - plb lock error p19 plb_wrburst plb i - plb burst write transfer p20 plb_rdburst plb i - plb burst read transfer p21 plb_wrpendreq plb i - plb pending bus write request p22 plb_rdpendreq plb i - plb pending bus read request p23 plb_wrpendpri[0:1] plb i - plb pending write request priority p24 plb_rdpendpri[0:1] plb i - plb pending read request priority p25 plb_reqpri[0:1] plb i - plb current request priority p26 plb_tattribute[0:15] plb i - plb transfer attribute plb slave interfa ce output signals p27 sl_addrack plb o 0 slave address acknowledge
DS707 april 19, 2010 www.xilinx.com 8 product specification logicore ip xps ps2 controller (v1.01b) p28 sl_ssize[0:1] plb o 0 slave data bus size p29 sl_wait plb o 0 slave wait p30 sl_rearbitrate plb o 0 slave bus rearbitrate p31 sl_wrdack plb o 0 slave write data acknowledge p32 sl_wrcomp plb o 0 slave write transfer complete p33 sl_rddbus[0: c_splb_dwidth - 1] plb o 0 slave read data bus p34 sl_rddack plb o 0 slave read data acknowledge p35 sl_rdcomp plb o 0 slave read transfer complete p36 sl_mbusy[0:c_splb_num_ masters - 1] plb o 0 slave busy p37 sl_mwrerr[0:c_splb_num_ masters - 1] plb o 0 slave write error p38 sl_mrderr[0:c_splb_num_ masters - 1] plb o 0 slave read error unused plb slave inte rface output signals p39 sl_wrbterm plb o 0 slave terminate write burst transfer p40 sl_rdwdaddr[0:3] plb o 0 slave read word address p41 sl_rdbterm plb o 0 slave terminate read burst transfer p42 sl_mirq[0: c_splb_num_ masters - 1] plb o 0 master interrupt request xps ps2 controller signals p43 ps2_1_data ps2 i/o z bi-directional port1 data p44 ps2_1_clk ps2 i/o z bi-directional port1 clock p45 ps2_2_data ps2 i/o z bi-directional port2 data p46 ps2_2_clk ps2 i/o z bi-directional port2 clock p47 ip2intc_irpt_1 ps2 o 0 active high level triggered interrupt signal from port1 p48 ip2intc_irpt_2 ps2 o 0 active high level triggered interrupt signal from port2 ta bl e 1 : xps ps2 controller i/o signal description (cont?d) port signal name interface i/o initial state description
DS707 april 19, 2010 www.xilinx.com 9 product specification logicore ip xps ps2 controller (v1.01b) xps ps2 controller design parameters to allow the user to create a xps ps2 controller that is uniquely tailored for the user?s system, certain features are parameterizable in the xps ps2 controller design. this allows the user to have a design that utilizes only the resources required by the system and runs at the best po ssible performance. the features that are parameterizable in the xps ps2 controller core are as shown in ta bl e 2 . ta bl e 2 : xps ps2 controller design parameters generic feature/description parameter name allowable values default value vhdl type system parameter g1 target fpga family c_family aspartan3, spartan3, spartan3a, spartan3e, spartan3adsp, virtex4, virtex5, virtex5fx, aspartan3e, aspartan3a, aspartan3adsp, qvirtex4, qrvirtex4, spartan6, virtex6, virtex6cx,spartan6 spartan3 string plb parameters g2 xps ps2 controller base address c_baseaddr valid address (2) none (1) std_logic_vector g3 xps ps2 controller high address c_highaddr valid address (2) none (1) std_logic_vector g4 plb address width c_splb_awidth 32 32 integer g5 plb data width c_splb_dwidth 32, 64, 128 32 integer g6 selects point-to-point or shared plb topology c_splb_p2p 0 = shared bus topology 0 integer g7 plb master id bus width c_splb_mid_width log 2 (c_splb_ num_masters) with a minimum value of 1 1 integer g8 number of plb masters c_splb_num_ masters 1 - 16 1 integer g9 width of the slave data bus c_splb_native_ dwidth 32 32 integer g10 enable burst support c_splb_support_ bursts 0 0 integers xps ps2 controller features g11 use dual channel c_is_dual 0/1 0 integer g12 plb clock frequency c_splb_clk_ freq_hz valid frequency (3) 100000000 integer 1. no default value will be specified to insure that the actual value is set, i.e., if the value is not set, a compiler error wi ll be generated 2. c_baseaddr must be a multiple of the range size, wher e the range size is c_highaddr - c_baseaddr + 1 and must be a power of two large enough to accommodate all of the registers 3. valid frequency in hertz, depending on the device family. for spartan3 devices, the frequency can be a maximum of 100mhz. for virtex4 devices, a maximum of 125mhz and for virtex5 devices, a maximum of 150mhz
DS707 april 19, 2010 www.xilinx.com 10 product specification logicore ip xps ps2 controller (v1.01b) allowable parameter combinations the address-range size specified by c_ baseaddr and c_highaddr must be a power of 2, and must be at least 0x40 in the single port mode. the address range should be at least 0x1040 in the dual port mode, so that the registers associated with the second port are also accommodated. for example, if c_baseaddr = 0xe0000000, c_highaddr must be at least = 0xe000003f, when c_is_dual = 0. the address range size when c_is_dual = 0 is (0xe 000003f - 0xe0000000) + 1 = 0x40. and c_highaddr must be at least = 0xe000103f, when c_is_dual = 1. the address range when c_is_dual = 1 is (0xe000103f - 0xe0000000) + 1 = 0x1040. xps ps2 controller parameter - port dependencies the dependencies between the xps ps2 controller core design parameters and i/o signals are described in table 3 . in addition, when certain features are parameterized out of the design, the related logic will no longer be a part of the design. the unused input signals and related output signals are set to a specified value. ta bl e 3 : xps ps2 controller design para meter - port dependencies generic or port name affects depends rela tionship description design parameters g4 c_splb_awidth p3 - affects number of bits in address bus g5 c_splb_dwidth p7,p10, p33 - affects number of bits in data bus g7 c_splb_mid_width p5 g8 affects the width of current master identifier signals and depends on log 2 (c_splb_num_masters) with a minimum value of 1 g8 c_splb_num_masters p36,p37, p38,p42 - affects the width of busy and error signals. g11 c_is_dual p45,p46, p48 when c_is _dual is 1, port2 is created i/o signals p3 plb_abus[0: c_splb_awidth - 1] - g4 width varies with the size of the plb address bus p5 plb_masterid[0: c_splb_mid_width- 1] -g7 width varies with the size of the plb master identifier bus p7 plb_be[0: (c_splb_dwidth/8)-1] - g5 width varies with the size of the plb data bus p10 plb_wrdbus[0: c_ splb_dwidth - 1] - g5 width varies with the size of the plb data bus p32 sl_rddbus[0: c_splb_dwidth - 1] - g5 width varies with the size of the plb data bus p36 sl_mbusy[0: c_splb_num_ masters - 1] -g8 width varies with the size of the plb number of masters p37 sl_mwrerr[0: c_splb_num_ masters - 1] -g8 width varies with the size of the plb number of masters
DS707 april 19, 2010 www.xilinx.com 11 product specification logicore ip xps ps2 controller (v1.01b) xps ps2 controller register descriptions there are eight internal registers in the xps ps2 controller design as shown in ta ble 4 . these registers are implemented in the ps2_reg interface module. the memory map of the xps ps2 controller design is determined by setting the c_baseaddr parameter. the internal registe rs of the xps ps2 controller are at a fixed offset from the base address. the xps ps2 co ntroller internal registers and their offset are listed in table 4 . table 5 shows the xps ps2 port1 interrupt registers and their of fset from the base address of xps ps2 memory map. p38 sl_mrderr[0: c_splb_num_ masters - 1] -g8 width varies with the size of the plb number of masters p42 sl_mirq[0: c_splb_num_ masters - 1] -g8 width varies with the size of the plb number of masters p45 ps2_2_data - g11 depends on whether the dual channel is enabled p46 ps2_2_clk - g11 depends on whether the dual channel is enabled ta bl e 4 : xps ps2 controller internal registers register name description base address + offset (hex) access srst_1 xps ps2 port1 software reset register c_baseaddr + 0x0000 write status_reg1 xps ps2 port1 status register c_baseaddr + 0x0004 read rx1_data xps ps2 port1 receive data register c_baseaddr + 0x0008 read tx1_data xps ps2 port1 transmit data register c_baseaddr + 0x000c write srst_2 xps ps2 port2 software reset register c_baseaddr + 0x1000 write status_reg2 xps ps2 port2 status register c_baseaddr + 0x1004 read rx2_data xps ps2 port2 receive data register c_baseaddr + 0x1008 read tx2_data xps ps2 port2 transmit data register c_baseaddr + 0x100c write 1. writing into a read-only register or r eading a write-only register would generate an error. this would be communicated to the plb interface module. such a transaction would not be a valid transaction. 2. the default value of all the above mentioned registers is zeros. ta bl e 5 : ps2 port1 interrupt registers register name base address + offset (hex) access xps ps2 port1 global interrupt enable register (gie_1) c_baseaddr + 0x002c read/write xps ps2 port1 interrupt status regi ster (ipisr_1) c_basea ddr + 0x0030 read/tow (1) xps ps2 port1 interrupt enable register (ipier_1) c_baseaddr + 0x0038 read/write 1. tow = toggle on write. writing a ?1? to a bit position within the register causes the corresponding bit position in the regis ter to toggle. ta bl e 3 : xps ps2 controller design para meter - port dependencies (cont?d) generic or port name affects depends rela tionship description
DS707 april 19, 2010 www.xilinx.com 12 product specification logicore ip xps ps2 controller (v1.01b) table 6 shows the xps ps2 port2 interrupt registers and their offset from the base address of xps ps2 memory map. as indicated in table 6 , the interrupt/status/data registers of ps 2 port1 start at the base address and the interrupt/status/data registers of the ps 2 port2 start at base address + 0x1000. depending on whether the parameter c_is_dual is 1 or 0, the status/data registers srst_2, status_reg2, rx2_data and tx2_data and the port2 interrupt registers gie_2, ipisr_2 and ipier_2 are included or removed respectively. xps portx software reset register (srst_x) the xps ps2 controller has internal software reset regist er (srst_x) for each of its two ports, resetting the registers independently. the reset register is shown in figure 4 . it is a write only register addressed at an offset 0x0 from base address c_baseaddr/c_bas eaddr+0x10. the bit definitions of this register are as shown in table 7 . xps ps2 portx status register the xps ps2 portx status register indicates the status of the ps2 portx while transmitting and receiving data packets. figure 5 and table 8 give a more detailed description of the status bits which do the same. ta bl e 6 : ps2 port2 interrupt registers register name base address + offset (hex) access xps ps2 port2 global interrupt enable register (gie_2) c_baseaddr + 0x102c read/write xps ps2 port2 interrupt status register (ipisr_2) c_baseaddr + 0x1030 read/tow (1) xps ps2 port2 interrupt enable register (ipier_2) c_baseaddr + 0x1038 read/write 1. tow = toggle on write. writing a ?1? to a bit position within the register causes the corresponding bit position in the regis ter to toggle. x-ref target - figure 4 figure 4: software reset register (srst) ta bl e 7 : srst register bit definitions bits name core access reset value description 0 - 31 srst_x write n/a software reset a write of 0x0000000a causes reset of the xps ps2 contro ller. a write of any other value has undefined effect and returns a bus error. a read of this register returns zero. x-ref target - figure 5 figure 5: xps ps2 status register 3 1 0 r s t d s 707_04_041910 un us ed txx_full_ s tat u s rxx_full_ s tat u s 3 1 0 3 0 29 d s 707_05_041910
DS707 april 19, 2010 www.xilinx.com 13 product specification logicore ip xps ps2 controller (v1.01b) xps ps2 portx receive data register xps ps2 portx receive data register is used to read the data line during device-to- host communication. the device writes the data into this register and the host reads back the data from this register to perform the appropriate functions. table 9 gives a detailed description of the xps ps2 portx receive data register. the xps ps2 portx receive data register is shown in figure 6 . xps ps2 portx transmit data register xps ps2 portx transmit data register is drive the data line during host-to-device communication. the host writes the data into this register and the sie transmits the data on the data line for the devi ce to perform the necessary function. ta ble 10 gives a detailed description of the xps ps2 portx transmit data register. the xps ps2 portx transmit data register is shown in figure 7 table 8: xps ps2 status register description bit(s) name core access reset value description 0 to 29 unused n/a 0 unused 30 txx_full_status read ?0? ps2 portx sie is busy. this field is set when the data to be transmitted is written into the transmit register. this is field is cleared when the transmission is done. the software has no direct write permission to change this field, since this field is set by the state machine in the sie. however, the software can indirectly do that by using the soft reset register 31 rxx_full_status read ?0? this field is set when the data packet is received by the portx sie and is waiting for the host to read this data packet. this field is cleared once the data packet is read by the host. the software has no direct write permission to change this field, since this field is set by the state machine in the sie. however, the software can indirectly do that by using the soft reset register x-ref target - figure 6 figure 6: xps ps2 receive data register ta bl e 9 : xps ps2 receive data re gister description bit(s) name core access reset value description 0 to 23 unused n/a 0 unused 24 to 31 rxx_data read 0 ps2 portx receive data from the device to host x-ref target - figure 7 figure 7: xps ps2 transmit data register 0 2 3 un us ed rxx_data 3 1 24 2 3 0 d s 707_06_041910 0 2 3 un us ed t x x _ data 3 1 24 2 3 0 d s 707_07_041910
DS707 april 19, 2010 www.xilinx.com 14 product specification logicore ip xps ps2 controller (v1.01b) xps ps2 controller interrupts the interrupts generated by xps ps2 controller are manage d by the interrupt service controller (isc). this unit provides many of the features commonly provided for in terrupt handling.to support in terrupt capability for the two ps2 ports, the plb interface module implements the following registers: ? global interrupt enable register (gie) ? ip interrupt enable register (ip ier) ? ip interrupt status register (ip isr) the ip ier implements independent interrupt enable bi t for each ps2 port while the global interrupt enable register provides the master enable/disable for the in terrupt output to the processor. the ip isr implements independent interrupt status bit for each ps2 port. the ip isr provides read and toggle-on-write access. the toggle-on-write mechanism for the ip interrupt status register avoids the requirement on the user interrupt service routine to perform read-modify-write operation to clear the status bit of the interrupt. read-modify-write operations can lead to inadvertent clearing of interrupts captured in the time period between the read and write operations. please refer to the processor ip reference guide under part 1 for a complete description of the gie, ipier and ipisr. xps ps2 portx global interrupt enable register (gie_x) the device global interrupt enable register provides th e final enable/disable for the interrupt output to the processor and resides in the plb interface module. this is a single bit read/write register as shown in figure 8 . table 11 shows the gie bit definitions. ta bl e 1 0 : xps ps2 transmit data register description bit(s) name core access r eset value description 0 to 23 unused n/a 0 unused 24 to 31 txx_data write 0 ps2 portx transmit data from the host to device x-ref target - figure 8 figure 8: device global interrupt enable register ta bl e 1 1 : device global interrupt enable register (gie) bit definitions bit(s) name core access reset value description 0 global interrupt enable read/write ?0? master enable for routing device interrupt to the system interrupt controller. ?1? = enabled ?0? = disabled 1 to 31 unused n/a 0 unused 01 3 1 un us ed glo ba l interr u pt en ab le d s 707_0 8 _041910
DS707 april 19, 2010 www.xilinx.com 15 product specification logicore ip xps ps2 controller (v1.01b) xps ps2 portx interrupt status a nd interrupt enable registers xps ps2 portx interrupt status register (ipisr_x) and xps ps2 portx interrupt enable register (ipier_x), respectively. see figure 9 , table 12 and table 13 . x-ref target - figure 9 figure 9: interrupt status and interrupt enable register ta bl e 1 2 : xps ps2 portx interrupt status re gister (ipisr) bit definitions bit(s) name core access reset value description 0 to 25 unused n/a 0 unused 26 rxx_full read/tow ?0? portx rx data register full this bit is set by the ps2 sie, when it has received a data packet 27 rxx_err read/tow ?0? portx rx data error this bit is set by the ps2 sie, when it has received a bad packet 28 rxx_ovf read/tow ?0? portx rx data register overflow this bit is set by the ps2 sie, when a data packet is overwritten before the previous data was read 29 txx_ackf read/tow ?0? portx tx data acknowledge received this bit is set by the ps2 sie, when it has completed the transmission of a packet and received an acknowledgement from the ps2 device 30 txx_noack read/tow ?0? portx tx data acknowledge not received this bit is set by the ps2 sie, when it has completed transmission of a packet and has not received an acknowledgement from the ps2 device 31 wdtx_tout read/tow ?0? portx watchdog timer timeout this bit is set by the ps2 sie, when it has not received the clock from the ps2 device while transmission of a packet ta bl e 1 3 : xps ps2 portx interrupt enable re gister (ipier) bit definitions bit(s) name core access reset value description 0 to 25 unused n/a 0 unused 26 rxx_full read/write ?0? enable/disable portx rx data register full interrupt ?1? = enabled ?0? = disabled (masked) 27 rxx_err read/write ?0? enable/disable portx rx data error interrupt ?1? = enabled ?0? = disabled (masked) un us ed rxx_full rxx_err rxx_ovf txx_ackf txx_noack wdtx_tout 25 26 27 2 8 29 3 0 3 1 0 d s 707_09_041910
DS707 april 19, 2010 www.xilinx.com 16 product specification logicore ip xps ps2 controller (v1.01b) design implementation target technology the target technology is an fpga listed in the supported device family field of the logicore facts table. device utilization and performance benchmarks core performance because the xps ps2 controller core will be used with other design modules in the fpga, the utilization and timing numbers reported in this section are estimates only. when the xps ps2 controller core is combined with other designs in the system, the utilization of fpga resources an d timing of the xps ps2 contro ller design will vary from the results reported here. the xps ps2 controller resource utilization for various parameter combinations measured with the virtex-4 fpga as the target device are detailed in table 14 . 28 rxx_ovf read/write ?0? enable/disable portx rx data register overflow interrupt ?1? = enabled ?0? = disabled (masked) 29 txx_ackf read/write ?0? enable/disable portx tx data acknowledge received interrupt ?1? = enabled ?0? = disabled (masked) 30 txx_noack read/write ?0? enable/disable portx tx data acknowledge not received interrupt ?1? = enabled ?0? = disabled (masked) 31 wdtx_tout read/write ?0? enable/disable portx watch dog timer timeout interrupt ?1? = enabled ?0? = disabled (masked) ta bl e 1 4 : performance and resource utilization benchmarks for a v irtex-4 fpga (xc4vfx60-10-ff672) parameter values device resources performance c_is_dual slices slice flip-flops luts f max (mhz) 0 451 367 465 129 1 785 616 844 132 ta bl e 1 3 : xps ps2 portx interrupt enable re gister (ipier) bit definitions bit(s) name core access reset value description
DS707 april 19, 2010 www.xilinx.com 17 product specification logicore ip xps ps2 controller (v1.01b) the xps ps2 controller resource utilization for various parameter combinations measured with the virtex-5 fpga as the target device are detailed in table 15 . the xps ps2 controller resource utilization for variou s parameter combinations me asured with the spartan-3 fpga as the target device are detailed in table 16 . the xps ps2 controller resource utilization for various parameter combinations measured with the virtex-6 fpga as the target device are detailed in table 17 . the xps ps2 controller resource utilization for variou s parameter combinations me asured with the spartan-6 fpga as the target device are detailed in table 18 . ta bl e 1 5 : performance and resource utilization benchmarks for a v irtex-5 fpga (xc5vlx50t-1-ff665) parameter values device resources performance c_is_dual slices slice flip-flops luts f max (mhz) 0 197 367 342 174 1 332 614 653 175 ta bl e 1 6 : performance and resource utilization benchmarks for aspa rtan-3 fpga (xc3sd3400a-4-cs484) parameter values device resources performance c_is_dual slices slice flip-flops luts f max (mhz) 0 427 367 434 106 1 701 614 811 105 ta bl e 1 7 : performance and resource utilization benchmarks for a virtex -6 fpga (xc6vlx130t-1-ff1156) parameter values device resources performance c_is_dual slices slice flip-flops luts f max (mhz) 0 156 369 404 239 1 262 614 757 210 ta bl e 1 8 : performance and resource utilization benchmarks for a spa rtan-6 fpga (xc6slx150t-2-fgg900) parameter values device resources performance c_is_dual slices slice flip-flops luts f max (mhz) 0 183 370 404 134 1 304 614 743 121
DS707 april 19, 2010 www.xilinx.com 18 product specification logicore ip xps ps2 controller (v1.01b) system performance to measure the system performance (fmax) of this core, this core was added to a virtex-4 fpga system, a virtex-5 fpga system, a spartan-3a fpga system, a virtex-6 fp ga system, and a spartan-6 fpga system as the device under test (dut) are shown in figure 10 , figure 11 , figure 12 , figure 13 and figure 14 . x-ref target - figure 10 figure 10: virtex-4 fx fpga system with the xps ps2 controller as the dut x-ref target - figure 11 figure 11: virtex-5 lx fpga system with the xps ps2 controller as the dut x-ref target - figure 12 figure 12: spartan-3a fpga system with the xps ps2 controller as the dut powerpc 405 proce ss or mpmc xp s cdma xp s uart lite xp s gpio xp s intc xp s bram dplb1 iplb1 dplb0 iplb0 xp s cdma plbv46 plbv46 plbv46 d s 707_10_041910 device under te s t microbl a ze proce ss or mpmc xp s cdma device under te s t (dut) xp s uart lite xp s gpio xp s intc xp s bram xp s cdma mdm xcl xcl plbv46 d s 707_11_041910 microbl a ze proce ss or mpmc xp s cdma xp s uart lite xp s gpio xp s intc xp s bram xp s cdma mdm plbv46 d s 707_12_041910 device under te s t (dut)
DS707 april 19, 2010 www.xilinx.com 19 product specification logicore ip xps ps2 controller (v1.01b) the target fpga was then filled with logic to drive the lut and bram utilization to approximately 70% and the i/o utilization to approximately 80%. using the default tool options and the slowest speed grade for the target fpga, the resulting target f max numbers are shown in ta ble 19 . the target f max is influenced by the exact system and is provided for guidance. it is not a guaranteed value across all systems. specification exceptions n/a x-ref target - figure 13 figure 13: virtex-6 fpga system with th e xps ps2 controller as the dut x-ref target - figure 14 figure 14: spartan-6 fpga system with the xps ps2 controller as the dut ta bl e 1 9 : xps ps2 controller core system performance target fpga target f max (mhz) s3a700 -4 90 v4fx60 -10 100 v5lx50t -1 125 s6lx45t -2 100 v6lx130t -1 150 microbl a ze proce ss or mpmc xp s cdma xp s uart lite xp s gpio xp s intc xp s bram d s 707_1 3 _041910 xp s cdma mdm xcl xcl plbv46 device under te s t (dut) microbl a ze proce ss or mpmc xp s cdma xp s uart lite xp s gpio xp s intc xp s bram d s 707_14_041910 xp s cdma mdm plbv46 device under te s t (dut)
DS707 april 19, 2010 www.xilinx.com 20 product specification logicore ip xps ps2 controller (v1.01b) reference documents 1. ibm coreconnect 128- bit processor local bus, architectural specification (v4.6). ordering information this xilinx logicore ip module is provided at no additional cost with the xilinx ise design suite embedded edition software under the terms of the xilinx end user license . the core is generated using the xilinx ise embedded edition software (edk). for more information, please visit the xps ps2 controller product web page. information about this and other xilinx lo gicore ip modules is available at the xilinx intellectual property page. for information on pricing and availability of other xilinx logicore modules and software, please contact your local xilinx sales representative . revision history notice of disclaimer xilinx is providing this design, code, or information (collectively, the ?information?) to you ? as-is ? with no warranty of any kind, express or implied. xilinx makes no representation that the information, or any particular implementation thereof, is free from any claims of infr ingement. you are responsible for obtaining any rights you may require for any implementation based on the informat ion. all specifications are subject to change without notice. xilinx expressly disclaims any wa rranty whatsoever with respect to the adequacy of the information or any imp lementation based thereon, including but not limited to any warranties or representations that th is implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. except as stated herein, none of the information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, ph otocopying, recording, or otherwise, without the prior written consent of xilinx. date version revision 04/17/07 1.0 initial xilinx release 7/25/08 1.1 added qpro virtex-4 hi-rel and qpro virtex-4 rad tolerant support 4/24/09 1.2 replaced references to supported device families and tool name(s) with hyperlink to pdf file 7/20/09 1.3 s6/v6 resource utilization tables added 01/13/10 1.4 fixed signal missing from sensitivity list issue and updated the fmax and resource utilization tables 02/04/10 1.5 updated the fmax and resource utilization tables for spartan6 and virtex6 familes 4/19/10 1.6 updated for 12.1 release.

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